spi: support controllers with limited transfer size capabilities

Hardware / Coreboot - Vadim Bendebury [chromium.org] - 13 April 2015 06:01 UTC

Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI read and write transactions. Limiting transfer size in the wrapper allows to provide the API user with unlimited transfer size transactions.

The tranfer size limitation is added to the spi_slave structure, which is set up by the controller driver. The value of zero in this field means 'unlimited transfer size'. It will work with existion drivers, as they all either keep structures in the bss segment, or initialize them to all zeros.

This patch addresses the problem for reads only, as coreboot is not expected to require to write long chunks into SPI devices.

BRANCH=none BUG=chrome-os-partner:32441, chrome-os-partner:31438 TEST=set transfer size limit to artificially low value (4K) and observed proper operation on both Pistachio and ipq8086: both Storm and Urara booted through romstage and ramstage.

Change-Id: Ibb96aa499c3eec458c94bf1193fbbbf5f54e1477

f9ff353 spi: support controllers with limited transfer size capabilities
src/drivers/spi/spi_flash.c | 44 +++++++++++++++++++++-------------
src/drivers/spi/spi_flash_internal.h | 14 -----------
src/include/spi-generic.h | 5 ++++
src/soc/imgtec/pistachio/spi.c | 5 ++++
4 files changed, 37 insertions(+), 31 deletions(-)

Upstream: review.coreboot.org

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