Set elements:- UART1 clock dividers and MFIOs- SPIM1 clock dividers and MFIOs- USB clock dividers- System clock divider- System PLL- MIPS CPU PLL
BUG=chrome-os-partner:31438 TEST=tested on Pisachio bring up board; UART, SPI NOR, SPI NAND, and USB have proper functionality. BRANCH=none
Change-Id: Ib01186a652fd59295a4cafc3ca99b94aa9564f74
b3f666b urara: Configure clocks and MFIOs
src/mainboard/google/urara/Kconfig | 4 +
src/mainboard/google/urara/bootblock.c | 142 ++++++++++
src/soc/imgtec/pistachio/Makefile.inc | 1 +
src/soc/imgtec/pistachio/clocks.c | 344 +++++++++++++++++++++++++
src/soc/imgtec/pistachio/include/soc/clocks.h | 39 +++
5 files changed, 530 insertions(+)
Upstream: review.coreboot.org