x86: add coreboot table entry for TSC info

Hardware / Coreboot - Aaron Durbin [chromium.org] - 19 February 2016 12:50 UTC

The 8254 (Programmable Interrupt Timer) is becoming optional on x86 platforms -- either from saving power or not including it at all. To allow a payload to still use a TSC without doing calibration provide the TSC frequency information in the coreboot tables. That data is provided by code/logic already employed by platform. If tsc_freq_mhz() returns 0 or CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table record isn't created.

BUG=chrome-os-partner:50214 BRANCH=glados TEST=With all subsequent patches confirmed TSC is picked up in libpayload.

Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971

e0969ae x86: add coreboot table entry for TSC info
src/arch/x86/cpu.c | 18 ++++++++++++++++++
src/commonlib/include/commonlib/coreboot_tables.h | 8 ++++++++
2 files changed, 26 insertions(+)

Upstream: review.coreboot.org

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