i965: Don't add barrier deps for FB write messages

Graphics / Mesa 3D Graphics Library / Mesa - Kenneth Graunke [whitecape.org] - 8 February 2016 18:59 UTC

There are never render target reads, so there are no scheduling hazards.

Giving the extra flexibility to the scheduler makes it possible to do FB writes as soon as their sources are available, reducing register pressure. It also makes it possible to do the payload setup for more than one FB write message at a time, which could better hide latency.

shader-db results on Skylake:

total instructions in shared programs: 9110254 -> 9110211 (-0.00%) instructions in affected programs: 2898 -> 2855 (-1.48%) helped: 3 HURT: 0 LOST: 0 GAINED: 1

A reduction in instruction counts is surprising, but legitimate: the three shaders helped were spilling, and reducing register pressure allowed us to issue fewer spills/fills.

total cycles in shared programs: 69035108 -> 68928820 (-0.15%) cycles in affected programs: 4412402 -> 4306114 (-2.41%) helped: 4457 HURT: 213

d0e1d6b i965: Don't add barrier deps for FB write messages.
.../drivers/dri/i965/brw_schedule_instructions.cpp | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

Upstream: cgit.freedesktop.org


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