i965: Enable L3 caching of buffer surfaces

Graphics / Mesa 3D Graphics Library / Mesa - Francisco Jerez [riseup.net] - 31 January 2015 09:01 UTC

And remove the mocs argument of the emit_buffer_surface_state vtbl hook. Its semantics vary greatly from one generation to another, so it kind of encourages the caller to pass 0 which is the only valid setting across generations. After this commit the hardware-specific code decides what the best cacheability settings are for buffer surfaces, just like we do for textures.

This together with some additional changes coming is expected to improve performance of pull constants, buffer textures, atomic counters and image objects on Gen7 and up.

11f5d8a i965: Enable L3 caching of buffer surfaces.
src/mesa/drivers/dri/i965/brw_context.h | 1 -
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 +---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 4 +---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 +--
4 files changed, 3 insertions(+), 9 deletions(-)

Upstream: cgit.freedesktop.org

  • Share