i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.

Graphics / Mesa 3D Graphics Library / Mesa - Kenneth Graunke [whitecape.org] - 4 January 2015 19:21 UTC

According to the documentation, we need to do a CS stall on every fourth PIPE_CONTROL command to avoid GPU hangs. The kernel does a CS stall between batches, so we only need to count the PIPE_CONTROLs in our batches.

v2: Get the generation check right (caught by Chris Wilson), combine the ++ with the check (suggested by Daniel Vetter).

d41cf9f i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 32 +++++++++++++++++++++++++
2 files changed, 34 insertions(+)

Upstream: cgit.freedesktop.org

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