i965: Make Broadwell HiZ path arrange for TC flushes

Graphics / Mesa 3D Graphics Library / Mesa - Kenneth Graunke [whitecape.org] - 22 April 2014 12:57 UTC

HiZ operations make the depth/render caches out of sync with the sampler caches. We need to arrange for a TC flush to happen before the target buffer is used by the sampler. Calling brw_render_cache_set_add_bo makes that happen.

On previous generations, brw_blorp_exec took care of flushing the texture cache by calling intel_batchbuffer_emit_mi_flush after doing any rendering. If we were to use the normal drawing path, then brw_postdraw_set_buffers_need_resolve would handle this.

On Broadwell, we don't use BLORP, and we don't emit a rectangle primitive via the normal drawing path. The 3DSTATE_WM_HZ_OP and PIPE_CONTROL implicitly make drawing happen. So, none of our existing code makes this flush happen - we need to do it directly.

Fixes 11 Piglit copyteximage subtests.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77223 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77226

34a6834 i965: Make Broadwell HiZ path arrange for TC flushes.
src/mesa/drivers/dri/i965/gen8_depth_state.c | 3 +++
1 file changed, 3 insertions(+)

Upstream: cgit.freedesktop.org

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