i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions

Graphics / Mesa 3D Graphics Library / Mesa - Kenneth Graunke [whitecape.org] - 23 April 2015 16:05 UTC

The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing.

intel_emit_linear_blit needs to handle blits that are not cacheline aligned, as we use it for arbitrary glBufferSubData calls and subrange mappings.

Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst pixel X offset field to represent the unaligned portion, and subtract that from the address so it's cacheline aligned.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521

8c17d53 i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
src/mesa/drivers/dri/i965/intel_blit.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)

Upstream: cgit.freedesktop.org

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