i965/state: Create separate dirty state bits for each pipeline

Graphics / Mesa 3D Graphics Library / Mesa - Jordan Justen [intel.com] - 31 March 2015 18:40 UTC

When clearing the state for a pipeline, we will save changed state for the other pipelines.

v3:
- Adjust brw_upload_pipeline_state
- Don't pull pipeline state bits into common state bits
- Don't clear pipeline state bits
- Adjust 'clear' phase
- brw_clear_dirty_bits is now brw_render_state_finished
- Move cross-pipeline state flagging to brw_pipeline_state_finished
- Move pipeline clears to brw_pipeline_state_finished

d70f4e6 i965/state: Create separate dirty state bits for each pipeline
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 101 +++++++++++++++++++-------
2 files changed, 75 insertions(+), 27 deletions(-)

Upstream: cgit.freedesktop.org

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