i965/vec4: Add register classes up to MAX_VGRF_SIZE.

Graphics / Mesa 3D Graphics Library / Mesa - Francisco Jerez [riseup.net] - 10 February 2015 11:09 UTC

In preparation for some send from GRF instructions that will require larger payloads.

78e9043 i965/vec4: Add register classes up to MAX_VGRF_SIZE.
src/mesa/drivers/dri/i965/brw_fs.h | 3 ---
src/mesa/drivers/dri/i965/brw_shader.h | 3 +++
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 10 ++++++----
3 files changed, 9 insertions(+), 7 deletions(-)

Upstream: cgit.freedesktop.org

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