nir: Lower bitfield_extract

Graphics / Mesa 3D Graphics Library / Mesa - Matt Turner [gmail.com] - 14 January 2016 11:28 UTC

The OpenGL specifications for bitfieldExtract() says:

The result will be undefined if or is negative, or if the sum of and is greater than the number of bits used to store the operand.

Therefore passing bits=32, offset=0 is legal and defined in GLSL.

But the earlier SM5 ubfe/ibfe opcodes are specified to accept a bitfield width ranging from 0-31. As such, Intel and AMD instructions read only the low 5 bits of the width operand, making them not able to implement the GLSL-specified behavior directly.

This commit adds ubfe/ibfe operations from SM5 and a lowering pass for bitfield_extract to to handle the trivial case of = 32 as

bitfieldExtract: bits > 31 ? value : bfe(value, offset, bits)

Fixes: ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595

b82e26a nir: Lower bitfield_extract.
src/glsl/nir/nir.h | 1 +
src/glsl/nir/nir_opcodes.py | 31 ++++++++++++++++++++++++++++
src/glsl/nir/nir_opt_algebraic.py | 10 +++++++++
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 3 +++
src/mesa/drivers/dri/i965/brw_shader.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 +++
6 files changed, 49 insertions(+)

Upstream: cgit.freedesktop.org

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