baytrail: add code for supporting 2x ddr refresh rate

Hardware / Coreboot - Kane Chen [intel.com] - 10 April 2015 13:18 UTC

this code change provides a way to enable 2x refresh rate in RW image In baytrail, it enables 2x refresh rate by default

BUG=chrome-os-partner:35210 BRANCH=none TEST=check the register is set properly on rambi

Change-Id: I2a935b570c564986898b6c2064fc7ad43506dcba

ba9b7bf baytrail: add code for supporting 2x ddr refresh rate
src/soc/intel/baytrail/chip.h | 1 +
src/soc/intel/baytrail/ramstage.c | 13 +++++++++++++
2 files changed, 14 insertions(+)

Upstream: review.coreboot.org

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