broadwell: Fix devslp enable to use correct register

Hardware / Coreboot - Duncan Laurie [chromium.org] - 27 March 2015 00:00 UTC

This was a merge error when I was pulling in some of the code into this file I put it after the read of CAP2 but before it is modified and written back. In the end the DEVSLP bits are getting set/cleared that need to but the other bits in the register may be wrong. Also when enabling devslp set the devslp-present bit in each enabled port.

Also remove much of the 0:1f.2@0x98 setup and the attempt to write (the write once) CAP register that is already being written in the reference code.

BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus

Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662

1b0d5a3 broadwell: Fix devslp enable to use correct register
src/soc/intel/broadwell/sata.c | 45 ++++++++++++++++++----------------------
1 file changed, 20 insertions(+), 25 deletions(-)

Upstream: review.coreboot.org

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