broadwell: Fix PCIe ports programming sequences to enable HSIOPC

Hardware / Coreboot - Wenkai Du [intel.com] - 10 April 2015 13:09 UTC

HSIOPC/GPIO71 is used to control power to VCCHSIO, VCCUSB3PLL and
VCCSATA3PLL in S0. PCH will drive HSIOPC low when all the high speed I/O controllers (xHCI, SATA, GbE and PCIe) are idle.

This patch added a few additional PCIe programming steps as required in 535127 BIOS Writer Guide Rev 2.3.0 to enable this power saving mode.

BUG=none BRANCH=none TEST=tested on Paine watching GPIO71 toggling as expected

Change-Id: Ica6954c125ec3129e2659168f1f23dc861ce5708

8306761 broadwell: Fix PCIe ports programming sequences to enable HSIOPC
src/soc/intel/broadwell/pcie.c | 23 ++++++++++++++++++-----
src/soc/intel/broadwell/romstage/pch.c | 15 +++++++++++++++
2 files changed, 33 insertions(+), 5 deletions(-)

Upstream: review.coreboot.org

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