fsp1_1: add verstage support

Hardware / Coreboot - Aaron Durbin [chromium.org] - 14 October 2015 12:07 UTC

In order to support verstage the cache-as-ram split is taken advantage of such that verstage has the cache-as-ram setup and rosmtage has the cache-as-ram tear down path. The verstage proper just initializes the console and attempts to run romstage which triggers the vboot verification of the firmware. In order to pass the current FSP to use during romstage a global
variable in cache-as-ram is populated before returning to the assembly code which tears down cache-as-ram.

BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados with verstage support as well as
VBOOT_DYNAMIC_WORK_BUFFER with direct link in romstage.

Change-Id: I8de74a41387ac914b03c9da67fd80f8b91e9e7ca

909c512 fsp1_1: add verstage support
src/drivers/intel/fsp1_1/Makefile.inc | 5 ++
src/drivers/intel/fsp1_1/after_raminit.S | 4 +-
src/drivers/intel/fsp1_1/cache_as_ram.inc | 5 ++
src/drivers/intel/fsp1_1/car.c | 42 +++++++++++++++-
src/drivers/intel/fsp1_1/include/fsp/car.h | 1 +
src/drivers/intel/fsp1_1/romstage_after_verstage.S | 52 ++++++++++++++++++++
src/drivers/intel/fsp1_1/verstage.c | 28 +++++++++++
7 files changed, 134 insertions(+), 3 deletions(-)

Upstream: review.coreboot.org

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