intel/skylake: Implement native Cache-as-RAM (CAR)

Hardware / Coreboot - Subrata Banik [intel.com] - 29 January 2016 09:56 UTC

Now coreboot should do BIOS CAR setup along with NEM mode setup.

This patch also provides a mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size

[pg: updated to current upstream #defines]

BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3.

fbdc719 intel/skylake: Implement native Cache-as-RAM (CAR)
src/drivers/intel/fsp1_1/Kconfig | 8 -
src/drivers/intel/fsp1_1/after_raminit.S | 11 +-
src/drivers/intel/fsp1_1/cache_as_ram.inc | 19 +-
src/soc/intel/skylake/Kconfig | 10 +
src/soc/intel/skylake/include/soc/car_setup.S | 334 ++++++++++++++++++++++
src/soc/intel/skylake/include/soc/car_teardown.S | 54 ++++
src/soc/intel/skylake/romstage/romstage.c | 8 +
7 files changed, 427 insertions(+), 17 deletions(-)

Upstream: review.coreboot.org

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