This patch add functions to configure saradc clk and get saradc's raw value for each channel.
Currently add saradc to ramstage.
Please refer to TRM V0.3 Part 2 Chapter 18 for this IP.
BRANCH=none BUG=chrome-os-partner:51537 TEST=on kevin board, get the raw value 61 for channel 0, measure the ADC_IN0 as 0.109V, 61.0/1024 = 0.05957 0.109V/1.8V = 0.06056
Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e
bf48fbb rockchip: rk3399: support saradc
src/soc/rockchip/rk3399/Makefile.inc | 1 +
src/soc/rockchip/rk3399/clock.c | 18 +++++
src/soc/rockchip/rk3399/include/soc/clock.h | 1 +
src/soc/rockchip/rk3399/include/soc/saradc.h | 21 ++++++
src/soc/rockchip/rk3399/saradc.c | 93 ++++++++++++++++++++++++++
5 files changed, 134 insertions(+)
Upstream: review.coreboot.org