rockchip: spi: Add support for 16-bit APB reads

Hardware / Coreboot - Simon Glass [chromium.org] - 6 October 2016 14:50 UTC

With a SPI clock above about 24MHz the APB cannot keep up when doing individual byte transfers. Adjust the driver to use 16-bit reads when it can, to remove this bottleneck.

Any transaction which involves writing bytes still uses 8-bit transfers, to simplify the code. These are the transfers that are not time-critical since they tend to be small. The case that really matters is reading from SPI flash.

In general we can use 16-bit reads anytime we are transferring an even number of bytes. If the code detects an odd number of bytes, it tries to perform the operation in two steps: once in 16-bit mode with an even number of bytes, and once in 8-bit mode for the final byte. This allow us to use 16-bit reads even if asked to transfer (for example) 0xf423 bytes.

The limit on in_now and out_now is adjusted to 0xfffe to avoid an extra transfer when transferring ~>=64KB.

CQ-DEPEND=CL:383232 BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. I tested (with extra debugging) that the 16-bit case is being picked when it should be.

Change-Id: If5effae9a84e4de06537fd594bedf7f01d6a9c88

74fedbe rockchip: spi: Add support for 16-bit APB reads
src/soc/rockchip/common/spi.c | 53 +++++++++++++++++++++++++++++++----------
1 file changed, 40 insertions(+), 13 deletions(-)

Upstream: review.coreboot.org

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