tegra124: A couple clock fixes

Hardware / Coreboot - Gabe Black [google.com] - 15 December 2014 12:57 UTC

This fixes two problems with the clock configuration on tegra124. First, the macro which set up the i2c clocks tried to account for the fact that the i2c divisor's lsb represents 1.0 where it normally represents 0.5 by multiplying the target frequency by 2. That doesn't work, unfortunately, because the divisor is actually n + 1, and what n + 1 means depends on where the one's place is in the divisor.

Also, when calculating the divisor, the standard C division operator uses truncation to deal any remainder which tends to make the divisor smaller. That has the effect of making the output frequency higher than what was requested. Since it's usually safer to undershoot a frequency than overshoot it, this change makes those divisions round up instead.

Finally, the hand tuned temporary UART clock configuration was adjusted so that it still ends up with the same divisor. Without that, very early output from the bootblock is garbled, specifically the coreboot welcome banner, build timestamp, etc.

BUG=chrome-os-partner:27220 TEST=Built and booted on nyan. Used a logic analyzer to verify that the TPM i2c bus ran at 400KHz instead of 660KHz, and that the divisor was the expected
value. Measured boot time with and without EFS and verified that there was no change. Spot checked the output for errors and verified that none of the bootblock output was garbled. BRANCH=None

Had to add the stdlib.h from 89ed6c that hadn't been merged correctly.

Original-Change-Id: I7e948c361ed4bf58c608627d32f2e3424faea1fb

e5b2127 tegra124: A couple clock fixes.
src/include/stdlib.h | 8 ++++++++
src/soc/nvidia/tegra124/clock.c | 4 ++--
src/soc/nvidia/tegra124/include/soc/clock.h | 13 +++++++++----
3 files changed, 19 insertions(+), 6 deletions(-)

Upstream: review.coreboot.org

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