tegra124: change PLLD VCO calculation algorithm

Hardware / Coreboot - Ken Chang [nvidia.com] - 16 December 2014 18:07 UTC

The current algo sets dc shift clock divider to 5 and PLLD DIVP to 0, this is causing VCO out of the characterized range for some panels.

This CL changes the dc shift clock divider to 1 and calculates a proper DIVP to have the VCO inside the characterized range, i.e., 500MHz ~ 1000MHz.

BRANCH=none BUG=none TEST=Verify on below panels the pixel clock frequencies are correct. 1. AUO B133XTN01.3 (69.5 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 69.5 695 12/695/0 with: 69.5 139 3/139/2

2. AUO B140HTT01.0 (141 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: VCO (1410000000) out of range. Cannot support. with: 141 282 2/94/1

3. LG LP140WH8 (76.32 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.32 763.2 5/381/0 with: 76.3125 152.625 8/407/2

4. N116BGE-EA2 (76.42 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.40 764 3/191/0 with: 76.375 152.75 12/611/2

Original-Change-Id: Id4b3a4865acde37a97d7346ec88406f5237304eb

cbae0de tegra124: change PLLD VCO calculation algorithm
src/soc/nvidia/tegra124/clock.c | 23 +++++++++++++++--------
src/soc/nvidia/tegra124/display.c | 4 ++--
2 files changed, 17 insertions(+), 10 deletions(-)

Upstream: review.coreboot.org


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