x86: add standalone verstage support

Hardware / Coreboot - Aaron Durbin [chromium.org] - 14 October 2015 12:07 UTC

To support x86 verstage one needs a working buffer for
vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected
verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link.

BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage.

Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa

75c51d9 x86: add standalone verstage support
Makefile.inc | 1 +
src/arch/x86/Makefile.inc | 34 ++++++++++++++++++++++++-
src/arch/x86/bootblock_simple.c | 5 ++++
src/arch/x86/car.ld | 5 ++++
src/arch/x86/include/arch/early_variables.h | 17 +++++++++++++
src/arch/x86/include/arch/header.ld | 23 ++++++++++++++---
src/arch/x86/include/arch/memlayout.h | 4 +--
src/arch/x86/memlayout.ld | 7 +++++
src/console/Makefile.inc | 1 +
src/cpu/x86/lapic/Makefile.inc | 1 +
src/cpu/x86/tsc/Makefile.inc | 1 +
src/device/Makefile.inc | 1 +
src/drivers/pc80/tpm/Makefile.inc | 1 +
src/drivers/uart/Makefile.inc | 2 ++
src/lib/Makefile.inc | 2 ++
src/vendorcode/google/chromeos/vboot2/Kconfig | 2 +-
16 files changed, 99 insertions(+), 8 deletions(-)

Upstream: review.coreboot.org

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