MIPS32R6 and MIPS64R6 support

Programming / Compilers / GCC - mpf [138bc75d-0d04-0410-961f-82ee72b054a4] - 19 December 2014 14:17 UTC

gcc/

- config.gcc: Add mipsisa64r6 and mipsisa32r6 cpu support.
- config/mips/constraints.md (ZD): Add r6 restrictions.
- config/mips/gnu-user.h (DRIVER_SELF_SPECS): Add MIPS_ISA_LEVEL_SPEC.
- config/mips/loongson.md (div3, mod3): Move to mips.md.
- config/mips/mips-cpus.def (mips32r6, mips64r6): Define.
- config/mips/mips-modes.def (CCF): New mode.
- config/mips/mips-protos.h (mips_9bit_offset_address_p): New prototype.
- config/mips/mips-tables.opt: Regenerate.
- config/mips/mips.c (MIPS_JR): Use JALR $, for R6. (mips_rtx_cost_data): Add pseudo-processors W32 and W64. (mips_9bit_offset_address_p): New function. (mips_rtx_costs): Account for R6 multiply and FMA instructions. (mips_emit_compare): Implement R6 FPU comparisons. (mips_expand_conditional_move): Implement R6 selects. (mips_expand_conditional_trap): Account for removed trap immediate. (mips_expand_block_move): Disable inline move when LWL/LWR are removed. (mips_print_float_branch_condition): Update for R6 FPU branches. (mips_print_operand): Handle CCF mode compares. (mips_interrupt_extra_call_saved_reg_p): Do not attempt to callee-save MD_REGS for R6. (mips_hard_regno_mode_ok_p): Support CCF mode. (mips_mode_ok_for_mov_fmt_p): Likewise. (mips_secondary_reload_class): CCFmode can be loaded directly. (mips_set_fast_mult_zero_zero_p): Account for R6 multiply instructions. (mips_option_override): Ensure R6 is used with fp64. Set default mips_nan modes. Check for mips_nan support. Prevent DSP with R6. (mips_conditional_register_usage): Disable MD_REGS for R6. Disable FPSW for R6. (mips_mulsidi3_gen_fn): Support R6 multiply instructions.
- config/mips/mips.h (ISA_MIPS32R6, ISA_MIPS64R6): Define. (TARGET_CPU_CPP_BUILTINS): Rework for mips32/mips64. (ISA_HAS_JR): New macro. (ISA_HAS_HILO): New macro. (ISA_HAS_R6MUL): Likewise. (ISA_HAS_R6DMUL): Likewise. (ISA_HAS_R6DIV): Likewise. (ISA_HAS_R6DDIV): Likewise. (ISA_HAS_CCF): Likewise. (ISA_HAS_SEL): Likewise. (ISA_HAS_COND_TRAPI): Likewise. (ISA_HAS_FP_MADDF_MSUBF): Likewise. (ISA_HAS_LWL_LWR): Likewise. (ISA_HAS_IEEE_754_LEGACY): Likewise. (ISA_HAS_IEEE_754_2008): Likewise. (ISA_HAS_PREFETCH_9BIT): Likewise. (MIPSR6_9BIT_OFFSET_P): New macro. (BASE_DRIVER_SELF_SPECS): Use MIPS_ISA_DRIVER_SELF_SPECS. (DRIVER_SELF_SPECS): Use MIPS_ISA_LEVEL_SPEC. (MULTILIB_ISA_DEFAULT): Handle mips32r6 and mips64r6. (MIPS_ISA_LEVEL_SPEC): Likewise. (MIPS_ISA_SYNCI_SPEC): Likewise. (ISA_HAS_64BIT_REGS): Likewise. (ISA_HAS_BRANCHLIKELY): Likewise. (ISA_HAS_MUL3): Likewise. (ISA_HAS_DMULT): Likewise. (ISA_HAS_DDIV): Likewise. (ISA_HAS_DIV): Likewise. (ISA_HAS_MULT): Likewise. (ISA_HAS_FP_CONDMOVE): Likewise. (ISA_HAS_8CC): Likewise. (ISA_HAS_FP4): Likewise. (ISA_HAS_PAIRED_SINGLE): Likewise. (ISA_HAS_MADD_MSUB): Likewise. (ISA_HAS_FP_RECIP_RSQRT): Likewise.
- config/mips/mips.md (processor): Add w32 and w64. (FPCC): New mode iterator. (reg): Add CCF mode. (fpcmp): New mode attribute. (fcond): Add ordered, ltgt and ne codes. (fcond): Update code attribute. (sel): New code attribute. (selinv): Likewise. (ctrap4): Update condition. (*conditional_trap_reg): New define_insn. (*conditional_trap): Update condition. (mul3): Expand R6 multiply instructions. (mulsi3_highpart): Likewise. (muldi3_highpart): Likewise. (mul3_mul3_loongson): Rename... (mul3_mul3_hilo): To this. Add R6 mul instruction. (mulsidi3_32bit_r6): New expander. (mulsidi3_32bit): Restrict to pre-r6 multiplies. (mulsidi3_32bit_r4000): Likewise. (mulsidi3_64bit): Likewise. (mulsi3_highpart_internal): Likewise. (mulsidi3_64bit_r6dmul): New instruction. (mulsi3_highpart_r6): Likewise. (muldi3_highpart_r6): Likewise. (fma4): Likewise. (movccf): Likewise. (*sel_using_): Likewise. (*sel): Likewise. (div3): Moved from loongson.md. Add R6 instructions. (mod3): Likewise. (extvmisalign): Require ISA_HAS_LWL_LWR. (extzvmisalign): Likewise. (insvmisalign): Likewise. (mips_cache): Account for R6 displacement field sizes. (*branch_fp): Rename... (*branch_fp_): To this. Add CCFmode support. (*branch_fp_inverted): Rename... (*branch_fp_inverted_): To this. Add CCFmode support. (s_): Rename... (s__using_): To this. Add FCCmode condition support. (s_ swapped): Rename... (s__using_ swapped): To this. Add CCFmode condition support. (movcc GPR): Expand R6 selects. (movcc FPR): Expand R6 selects. (*tls_get_tp__split): Do not .set push for >= mips32r2.
- config/mips/netbsd.h (TARGET_CPU_CPP_BUILTINS): Update similarly to mips.h. (ASM_SPEC): Add mips32r6, mips64r6.
- config/mips/t-isa3264 (MULTILIB_OPTIONS, MULTILIB_DIRNAMES): Update for mips32r6/mips64r6.
- doc/invoke.texi: Document -mips32r6,-mips64r6.
- doc/md.texi: Update comment for ZD constraint.

libgcc/

- config.host: Support mipsisa32r6 and mipsisa64r6.
- config/mips/mips16.S: Do not build for R6.

gcc/testsuite/

- gcc.dg/torture/mips-hilo-2.c: Unconditionally pass for R6 onwards.
- gcc.dg/torture/pr19683-1.c: Likewise.
- gcc.target/mips/branch-cost-2.c: Require MOVN.
- gcc.target/mips/movcc-1.c: Likewise.
- gcc.target/mips/movcc-2.c: Likewise.
- gcc.target/mips/movcc-3.c: Likewise.
- gcc.target/mips/call-saved-4.c: Require LDC.
- gcc.target/mips/dmult-1.c: Require R5 or earlier.
- gcc.target/mips/fpcmp-1.c: Likewise.
- gcc.target/mips/fpcmp-2.c: Likewise.
- gcc.target/mips/neg-abs-2.c: Likewise.
- gcc.target/mips/timode-1.c: Likewise.
- gcc.target/mips/unaligned-1.c: Likewise.
- gcc.target/mips/madd-3.c: Require MADD.
- gcc.target/mips/madd-9.c: Likewise.
- gcc.target/mips/maddu-3.c: Likewise.
- gcc.target/mips/msub-3.c: Likewise.
- gcc.target/mips/msubu-3.c: Likewise.
- gcc.target/mips/mult-1.c: Require INS and not DMUL.
- gcc.target/mips/mips-ps-type-2.c: Require MADD.PS.
- gcc.target/mips/mips.exp (mips_option_groups): Add ins, dmul, ldc, movn, madd, maddps. (mips-dg-options): INS available from R2. LDC available from MIPS II, DMUL is present in octeon. Describe all features removed from R6.

78645e7 MIPS32R6 and MIPS64R6 support
gcc/ChangeLog | 123 +++++++
gcc/config.gcc | 26 +-
gcc/config/mips/constraints.md | 10 +-
gcc/config/mips/gnu-user.h | 1 +
gcc/config/mips/loongson.md | 30 --
gcc/config/mips/mips-cpus.def | 2 +
gcc/config/mips/mips-modes.def | 3 +
gcc/config/mips/mips-protos.h | 1 +
gcc/config/mips/mips-tables.opt | 406 ++++++++++++------------
gcc/config/mips/mips.c | 265 ++++++++++++++--
gcc/config/mips/mips.h | 139 +++++---
gcc/config/mips/mips.md | 280 +++++++++++++---
gcc/config/mips/netbsd.h | 25 +-
gcc/config/mips/t-isa3264 | 6 +-
gcc/doc/invoke.texi | 15 +-
gcc/doc/md.texi | 6 +-
gcc/testsuite/ChangeLog | 28 ++
gcc/testsuite/gcc.dg/torture/mips-hilo-2.c | 4 +
gcc/testsuite/gcc.dg/torture/pr19683-1.c | 4 +
gcc/testsuite/gcc.target/mips/args-3.c | 2 +-
gcc/testsuite/gcc.target/mips/branch-cost-2.c | 2 +-
gcc/testsuite/gcc.target/mips/call-saved-4.c | 2 +-
gcc/testsuite/gcc.target/mips/dmult-1.c | 2 +-
gcc/testsuite/gcc.target/mips/fpcmp-1.c | 2 +-
gcc/testsuite/gcc.target/mips/fpcmp-2.c | 2 +-
gcc/testsuite/gcc.target/mips/madd-3.c | 2 +-
gcc/testsuite/gcc.target/mips/madd-9.c | 2 +-
gcc/testsuite/gcc.target/mips/maddu-3.c | 2 +-
gcc/testsuite/gcc.target/mips/mips-ps-type-2.c | 2 +-
gcc/testsuite/gcc.target/mips/mips.exp | 66 +++-
gcc/testsuite/gcc.target/mips/movcc-1.c | 2 +-
gcc/testsuite/gcc.target/mips/movcc-2.c | 2 +-
gcc/testsuite/gcc.target/mips/movcc-3.c | 2 +-
gcc/testsuite/gcc.target/mips/msub-3.c | 2 +-
gcc/testsuite/gcc.target/mips/msubu-3.c | 2 +-
gcc/testsuite/gcc.target/mips/mult-1.c | 2 +-
gcc/testsuite/gcc.target/mips/neg-abs-2.c | 2 +-
gcc/testsuite/gcc.target/mips/timode-1.c | 2 +-
gcc/testsuite/gcc.target/mips/unaligned-1.c | 2 +-
libgcc/ChangeLog | 5 +
libgcc/config.host | 4 +-
libgcc/config/mips/mips16.S | 9 +-
42 files changed, 1094 insertions(+), 402 deletions(-)

Upstream: gcc.gnu.org

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