pistachio: add DDR2 initialization code

Hardware / Coreboot - Ionela Voinescu [imgtec.com] - 17 April 2015 03:07 UTC

This is the intialization code specific to the Winbond W972GG6JB-25 part using Synopsys DDR uMCTL and DDR Phy.

This is DDR2 initialization code only (currently present on the bring up board). DDR3 initialization code will follow for boards having DDR3 memory.

The programming procedure that is executed at power up to bring up the uMCTL, PHY and memories into a state where reads and writes to the memory can be performed is the following:

1. uPCTL (Universal DDR protocol controller) initialization The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH needed for driving the memory power-up sequence are programmed as a function of the internal timers clock frequency. Organization (memory chip specific) values are set (column/bank/row address width and number of ranks), together with other static values (latency, timing, power up configuration). All these values are static, provided by the datasheet, being determined by the memory type, size and frequency. 2. PHY initialization The PHY is programmed with datasheet provided values, specifying the initialization values for it to send to the external memory (timing parameters). Also, delay lines (DLL) and strength of drive pads are calibrated (based on external conditions: temperature,
voltage, noise) and locked. After that, the PHY goes through a trainig process (also dependent on the current conditions at boot time) to establish precise timing configuration between the DDR clock and DQS (data strobe) and between DQS and DQ (data). 3. Memory power up 4. Switch from configuration state to access state.

BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly DDR2 is also tested during chip sort. Corner cases (performace of DDR in different conditions) will be tested after the chip reaches a stable state.

BRANCH=none

Change-Id: I0093dc175d064aad03052d5281679b008c1bf012

d6aaca9 pistachio: add DDR2 initialization code
src/soc/imgtec/pistachio/Makefile.inc | 1 +
src/soc/imgtec/pistachio/ddr2_init.c | 669 +++++++++++++++++++++++
src/soc/imgtec/pistachio/include/soc/ddr_init.h | 25 +
src/soc/imgtec/pistachio/romstage.c | 10 +-
4 files changed, 704 insertions(+), 1 deletion(-)

Upstream: review.coreboot.org


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