pistachio: add SOC descriptor

Hardware / Coreboot - Vadim Bendebury [chromium.org] - 8 April 2015 19:32 UTC

With this descriptor added ramstage properly allocates memory resources and creates entries in coreboot table. This also allows to proceed to booting depthcharge, as it now can be loaded into the existing memory.

BRANCH=none BUG=chrome-os-partner:31438

TEST=with the set of patches applied the firmware properly finds depthcharge in CBFS, uncompresses it and attempts to start:


Booting payload fallback/payload from cbfs Loading segment from rom address 0x9b000058 code (compression=1) New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe Loading segment from rom address 0x9b000074 Entry Point 0x80124038 Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe lb: [0x0000000080000000, 0x0000000080013858) Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe using LZMA [ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090 Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054 dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129 Jumping to boot code at 80124038 ERROR: dropped a timestamp entry CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes entry = 80124038

Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175

f3bc026 pistachio: add SOC descriptor
src/mainboard/google/urara/devicetree.cb | 1 +
src/soc/imgtec/pistachio/Makefile.inc | 1 +
src/soc/imgtec/pistachio/soc.c | 48 ++++++++++++++++++++++++++++++
3 files changed, 50 insertions(+)

Upstream: review.coreboot.org

  • Share