pistachio: clean DDR2 initialization code

Hardware / Coreboot - Ionela Voinescu [imgtec.com] - 21 April 2015 01:26 UTC

The proper way to initialize DDR2 is for the PHY to automatically establish precise timing configuration through the training process. The alternative (used initially for testing) is no longer needed.

This change determined the removal of some local
variables as they ended up being used in one location only.

BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly. BRANCH=none

Change-Id: I31e9a8975d176a04061f9c84fe06cce850bb53b9

59074ff pistachio: clean DDR2 initialization code
src/soc/imgtec/pistachio/ddr2_init.c | 170 +++-------------------------------
1 file changed, 15 insertions(+), 155 deletions(-)

Upstream: review.coreboot.org

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