skylake: Add initial FSP2.0 support

Hardware / Coreboot - Rizwan Qureshi [intel.com] - 31 August 2016 13:02 UTC

Add Initial pieces of code to support fsp2.0 in skylake keeping the fsp1.1 flow intact.

The soc/romstage.h and soc/ramstage.h have a reference to fsp driver includes, so split these header files for each version of FSP driver.

Add the below files, car_stage.S: Add romstage entry point (car_stage_entry). This calls into romstage_fsp20.c and aslo handles the car teardown. romstage_fsp20.c: Call fsp_memory_init() and also has the callback for filling memory init parameters.

Also add monotonic_timer.c to verstage.

With this patchset and relevant change in kunimitsu mainboard, we are able to boot to romstage.

TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1 Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0

Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520

1222a73 skylake: Add initial FSP2.0 support
src/soc/intel/skylake/Kconfig | 1 +
src/soc/intel/skylake/Makefile.inc | 13 +-
src/soc/intel/skylake/chip_fsp20.c | 30 +++++
src/soc/intel/skylake/igd.c | 29 +----
src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 36 ++++++
src/soc/intel/skylake/include/fsp11/soc/romstage.h | 30 +++++
src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 39 ++++++
src/soc/intel/skylake/include/fsp20/soc/romstage.h | 30 +++++
src/soc/intel/skylake/include/soc/ramstage.h | 31 -----
src/soc/intel/skylake/include/soc/romstage.h | 30 -----
src/soc/intel/skylake/include/soc/smm.h | 1 -
src/soc/intel/skylake/include/soc/vr_config.h | 9 +-
src/soc/intel/skylake/memmap.c | 1 -
src/soc/intel/skylake/opregion.c | 49 ++++++++
src/soc/intel/skylake/reset.c | 32 +++++
src/soc/intel/skylake/romstage/Makefile.inc | 5 +-
src/soc/intel/skylake/romstage/car_stage.S | 131 ++++++++++++++++++++
src/soc/intel/skylake/romstage/romstage_fsp20.c | 44 +++++++
src/soc/intel/skylake/vr_config.c | 27 ++--
19 files changed, 460 insertions(+), 108 deletions(-)

Upstream: review.coreboot.org

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