skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init

Hardware / Coreboot - Rizwan Qureshi [intel.com] - 17 August 2016 23:26 UTC

Prepare Skylake for FSP2.0 support.

We do not use FSP-T in FSP2.0 driver, hence guard the FspTempRamInit call under a switch.

In addition to the current early PCH configuration program few more register, so all in all we do the following,
- Program and enable ACPI Base.
- Program and enable PWRM Base.
- Program TCO Base.
- Program Interrupt configuration registers.
- Program LPC IO decode range.
- Program SMBUS Base address and enable it.
- Enable upper 128 bytes of CMOS. And split the above programming into into smaller functions.

Also, as part of bootblock_pch_early_init we enable decoding for HPET range. This is needed for FspMemoryInit to store and retrieve a global data pointer.

And also move P2SB related definitions to a new header file.

TEST=Build and boot Kunimitsu

Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16

cf73c13 skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init
src/soc/intel/skylake/bootblock/bootblock.c | 11 +-
src/soc/intel/skylake/bootblock/pch.c | 9 ++
src/soc/intel/skylake/finalize.c | 7 +-
src/soc/intel/skylake/include/soc/bootblock.h | 6 ++
src/soc/intel/skylake/include/soc/p2sb.h | 28 +++++
src/soc/intel/skylake/include/soc/pcr.h | 5 +
src/soc/intel/skylake/include/soc/smbus.h | 12 ++-
src/soc/intel/skylake/romstage/pch.c | 143 ++++++++++++++++++++-----
8 files changed, 178 insertions(+), 43 deletions(-)

Upstream: review.coreboot.org

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